Presentations of Interest at DesignCon 2010

As I'm sure you already know, and as the official burb puts it "DesignCon is the definitive event for electronic design experts spanning chip, package, board, and system domains, addressing common issues in signal integrity, power management, interconnection, and design verification."

CST has been exhibiting at this event for several years now, demonstrating 3D simulation of the above components so that engineers can benefit from fully virtual design and optimization. For this year's show, we'll be showcasing our latest 2010 release and how it can benefit the DesignCon community. If you are attending, come by booth #307 on the show floor for a demo or take a look at our collaborative papers in the main conference.

Here's a selection of papers we are presenting:

• “Chip-to-Chip Communication Beyond 25 Gbps: Modeling and Realization” Jianmin Zhang, Qinghua Bill Chen, Kelvin Qiu, Cisco. Martin Schauer, Antonio Ciccomancini Scogna, and Gerardo Romo, CST of America Inc. Tuesday, February 2, 2:50 pm – 3:30 pm.


• “Efficient Modeling and Simulation for Package-PCB Co-Design and Co-Optimization” Martin Schauer, CST of America. Hong Ahn, Namhoon Kim, Chris Wyland, Paul Wu, Xilinx. Wednesday, February 3, 2:00 pm – 2:40 pm.


• “Full-Wave Time Domain Modeling of Interconnects” Martin Schauer, CST of America Inc. Alfred Neves, Tom Dagostino, Scott McMorrow, Teraspeed Consulting LLC. Thursday February 4, 9:50 am - 10:30 am.

DesignCon, Santa Clara Convention Center, Santa Clara, CA United States